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MXORG.ASC
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1993-08-28
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2KB
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50 lines
Figure 2: Memory organization in unchained 256-color modes (like
Mode X) (ASCII version)
by Robert Schmidt
(C) 1993 Ztiff Zox Softwear
Imagine that the screen looks the same as in figure 1a. A screen width
of 320 pixels is still assumed.
In VGA memory, the screen will be represented as follows:
Plane 0:
address: 0 10 70 79 (NOT 319!)
----------------------------------------
|0482604826048260 ..... 0482604826|
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Plane 1:
address: 0 10 70 79
----------------------------------------
|1593715937159371 ..... 1593715937|
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Plane 2:
address: 0 10 70 79
----------------------------------------
|2604826048260482 ..... 2604826048|
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Plane 3:
address: 0 10 70 79
----------------------------------------
|3715937159371593 ..... 3715937159|
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Note that if pixel i is in plane p, pixel i+1 is in plane (p+1)%4.
When the planes are unchained, we need to set the Write Plane Enable
register to select which planes should receive the data when writing,
or the Read Plane Select register when reading. As is evident, one
address in the video segment provides access to no less than FOUR
different pixels.